Talk:Cell (processor)

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Some wrong numbers?

There is a text "At 3.2 GHz, each SPE gives a theoretical 256 GFLOPS of single precision performance. The PPE's VMX128 (AltiVec) unit is fully pipelined for double precision floating point and can complete two double precision operations per clock cycle, which translates to 6.4 GFLOPS at 3.2 GHz; or eight single precision operations per clock cycle, which translates to 256 GFLOPS at 3.2 GHz[7]." Well, this would give you 2.3 TFLOPS, while Cell spec. says 256 GFLOPS total... Also, 3.2 x 8 = 25.6, not 256.

From what i see this is actually an error on IBMs page. It says: "fully pipelined DP floating-point support in the PPE's VMX" - Since when does VMX support DP floats?

From GreenbDS -- please see http://www-128.ibm.com/developerworks/forums/dw_thread.jsp?forum=739&thread=136461&cat=46 The 200+ GFLOPS is accurate for the whole chip, not for "each SPU."

IBM Blade

Disclaimer: I work for IBM.

IBM has announced that general availability of an IBM dual-Cell blade (called "QS20") will commence on September 29. Here are the specs: http://www-03.ibm.com/technology/splash/qs20/

Also -- in terms of the lenghy list of links on the main page -- let me encourage you to point people to a portal to many of them: http://www.ibm.com/developerworks/power/cell.

I apologize that I am new to posting comments here. For tracking purposes, please call me "GreenbDS".

news

IBM have mentioned they may/will be making 'cells' with optimised double precision instructions on the SPU's. "JK: We used that first tape out to get the initial software up and running. There were modifications we did to the chip over time. The design center is still active and participating. Our roadmap shows we are continuing down the cost reduction path. We have a 65 nanometer part. We are continuing the cost reductions. We have another vector where we are going after more performance. We have talked about enhanced double-precision chips. Architecturally we have double precision but we will fully exploit that capability from a performance point of view. That will be useful in high-performance computing and open another set of markets" from http://blogs.mercurynews.com/aei/2006/10/the_playstation.html.

Perhaps in the future it will be neccessary to make the difference between the cell used in the PS3 and other cells - hope this is useful

Cell B.E. Chipset Shrinkage (90nm to 65nm to 45nm

Found info on the Cell processor shrinking down to 45nm, it will reduce power consumption 40% to to the older 65nm chipset. "Production is due to start in the summer so expect them on the shelves in time for Christmas (08')." There is also a handy graph detailing the differences in power use between 90nm, 65nm, 45nm chipsets. I got all this info from here: http://n4g.com/tech/News-118530.aspx

Graph of Cell B.E. Power Consumption

Graph of Cell B.E. Power Consumption